Diode Stress Test Array Circuit
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12
The circuit in the figure is used to evaluate both process- and reliability-induced defects in arrays of two-terminal devices, such as diodes or emitter-to-collector, or open base, transistors formed in a semiconductor substrate. The circuit includes a decoder coupled to a driver which is independently selectable and which is connected at its output to a word line of a diode array. The driver includes a first NPN transistor T1, with its collector gating a PNP transistor T2 and its emitter gating a second NPN transistor T3. The driver output, taken from the common point C between serially-connected diodes D1 and D2 to which word line 1 is connected, can either source or sink current.