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Multiplexed Primary Inputs Allow Conventional Testing of Tri State Logic

IP.com Disclosure Number: IPCOM000053664D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Moser, JJ Prilik, RJ [+details]

Abstract

This article teaches a method of testing tri-state off-chip driver circuits for the worst-case loading specification without requiring additional functional test patterns. The circuit utilized basically comprises the addition of a multiplexer between the logic and the tristate drivers being tested. As shown in the figure, a pair of primary logic inputs are entered into the system at nodes 10 and 11. These nodes are coupled to lines 12 and 13 leading directly to a logic controller 14 and via lines 15 and 16 directly to a multiplexer system 17. Entering this multiplexer 17 and parallel with the lines 15 and 16 are the lines 18 and 19 which feed the outputs of the logic system 14 to the multiplexer 17.