Electrical Measurements of Mask Runout and Mask To Wafer Misregistration on Product Wafers
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12
This invention allows for electrical measurement and separation of the overlay error components in semiconductor process technologies. The disclosed technique requires a set of three structures to unambiguously determine mask runout and mask-to-wafer misregistration for each level of mask. The geometry and detail of the structure used for electrical measurement varies depending on the particular type of mask levels involved. Two distinct variations of these structures are required for measurement between diffusion mask levels. The concept can be adapted to allow the appropriate measurements between contact openings and underlying diffusion levels, metallization and the contact level, and overlap-type vias and underlying metal.