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High Speed Decimal Multipliers Disclosure Number: IPCOM000053694D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

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Pivnichny, JR [+details]


The array format of parallel multipliers make them particularly amenable to high density large-scale integration (LSI). The parallel multiplier (Fig. 1) uses individual recurring array elements (Fig. 2) which are simple to implement with a very dense circuit chip layout.