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A programmable logic array (PLA) includes bit-partitioning logic at the OR-array inputs, as well as at the AND-array inputs.
English (United States)
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PLA Having OR Array Bit Partitioning
A programmable logic array (PLA) includes bit-partitioning logic at the OR-
array inputs, as well as at the AND-array inputs.
PLA 10 has a conventional AND array 11 having product-term lines 12 which
are selectively connectible to decoded lines 13, as indicated by heavy dots 14.
Lines 13 are the outputs of partition logics 15, which decode input lines 16. For
example, a two-bit partition logic translates a group of two input lines 16 into a
group of four decoded lines 13 as follows: Input Lines (16) Decoded Lines (13) 0
0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0
Product-term lines 12 are coupled to OR-array 17, which is of conventional
design except that a further set of bit-partition logics 18 decode pairs of lines 12
into sets of four lines 19. Lines 20 couple decoded lines 19 to the Set/Reset
inputs of latches 21, whose outputs are the outputs 22 of PLA 10. Dots 23 show
the OR connections. Partition logics 18 may have other than two inputs and four
outputs; e.g., they may transform three input lines into eight linearly decoded
lines. Partition logics 15 may also be other than two-to-four line decoders, and
logics 15 may have different numbers of lines than logics 18.
The connections 14, 23 shown in the drawing illustrate the utility of the above
PLA organization. Expressed in a two-level IF/THEN/ELSE format, the function
implemented is: IF (:SEQ = 110000) AND (CONDA) THEN IF (CONDB) THEN
Reset X ELSE IF (CONDB) THEN Set...