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DC Limited Recording Code and Implementation Disclosure Number: IPCOM000053756D
Original Publication Date: 1981-Nov-01
Included in the Prior Art Database: 2005-Feb-12

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Rooney, JA [+details]


The encoding scheme is a Rate 8/16 (1, 5) code which utilizes the system shown in Fig. 1 in which R1 is an 8-bit register containing a dataword to be stored from the HOST system; E is an encoder which is shown in detail in Figs. 3 and 4; R2 is a 16-bit parallel-input, serial-output shift register; S is a storage device which includes recording and read back circuitry, and more particularly may include a magnetic recording disk 10; R3 is a 16-bit serial-input, parallel-output shift register; D is an decoder; and R4 is an 8-bit register containing the dataword which is being retrieved by the HOST system from the disk 10.