Browse Prior Art Database

Sample and Hold Switch

IP.com Disclosure Number: IPCOM000053761D
Original Publication Date: 1981-Nov-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Rae, JW [+details]

Abstract

Sample and hold circuits which can be integrated onto a single silicon chip generally suffer from inadequate isolation of the switching signal from the holding capacitor. While FETs (field-effect transistors) are commonly used as switches in such circuits, the parasitic capacitance between the gate and the FET channel couples significant energy into the output circuit when a fast sample pulse is used. Bipolar transistors suffer from the limitation that the base-emitter voltage may create an offset error. While the offset error can be overcome by cascading opposite polarity offsets, the cascaded stages can introduce an offset if they are not switched simultaneously.