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Machine cycles of a data processor are extended to accommodate slow operations. These operations are identified by a specific signal emitted by the processor's control section.
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Machine Cycle Extension in a Data Processor
Machine cycles of a data processor are extended to accommodate slow
operations. These operations are identified by a specific signal emitted by the
processor's control section.
In Fig. 1, processor 10 has a conventional control section 11, such as read-
only storage (ROS) or a programmable logic array (PLA). Control section 11
emits a variety of control signals 12 to conventional data path section 13 for
gating logic, registers, arithmetic units, and so forth. Data-flow section 13
communicates with other units over busses 14, and supplies instruction codes,
status signals, etc., to control section 11 over lines 15. Clock oscillator 16
supplies constant frequency pulses to cycle control 17, which produces non-
overlapping pulses P1,P2 for timing control section 11 and non-overlapping
pulses C1,C2 for timing data-flow section 13.
One of the output lines of the ROS or PLA in control section 11 is an Extend
(XTND) signal 18, which holds the current levels of the cycle signals
P1,P2,C1,C2 for a predetermined additional time interval.
Fig. 2 shows the relevant control signals for both a normal cycle 20 and
extended cycles 30. A rising edge 21 of C1 begins cycle 20. After a fixed interval
following the fall of C1, C2 rises at 22; a fixed interval after the fall of C2 defines
the end of cycle 20. Time 22 also fixes the rise 23 of a narrower P2 pulse. After
P2 falls, P1 rises at 24. The XTND signal is low during a normal cycle 2...