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Process for Producing a Controlled Slope in Polysilicon Using Reactive Ion Etching

IP.com Disclosure Number: IPCOM000053805D
Original Publication Date: 1981-Nov-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Bennett, RS Ephrath, LM [+details]

Abstract

In a double polysilicon FET process, it is desirable to produce a sloped etch profile in the first polysilicon layer. A sloped profile is compared in Fig. 1 with the vertical profile that is characteristic of reactive ion etching, and the isotropic profile that is characteristic of plasma and wet etching. It has been found that a sloped polysilicon etch profile may be obtained in a reactive ion etching system which has been modified by the addition of an independent counter electrode by powering the substrate electrode and the counter electrode simultaneously.