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Rapid Display of Logic Interconnection Diagrams

IP.com Disclosure Number: IPCOM000053877D
Original Publication Date: 1981-Nov-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Cesa, LJ Hitchcock, RB Kellerman, E [+details]

Abstract

Described herein is a method for rapidly drawing logic blocks and their interconnections. A feature of the central algorithm is that the placement of the blocks is determined in such a way that the drawing of the interconnections can be done without extensive line routing. The algorithm is only applicable to feedback-free logic consisting exclusively of one-output blocks. Step 1 -- Levelize. Assign to each block the maximal distance to a P1 (primary input). This "level" will be used as the number of the column where the block will be drawn. Step 2 -- Determine the range for each block. The range for a block is a pair of integers, the first integer is set to the level of the block, and the second one is set to one less than the level of the go-to block furthest to the right of the given block.