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Static Cell Array Circuit to Enable Write by Turning Off the Cell Load Devices Disclosure Number: IPCOM000053894D
Original Publication Date: 1981-Nov-01
Included in the Prior Art Database: 2005-Feb-12

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Eardley, DB [+details]


A technique is described which allows the operation of an array of static memory cells with a single low voltage chip power supply of, e.g., 2 V. The proposal may be applied to an array (Fig. 1) of conventional memory cells (Fig. 2) each containing two cross-coupled NPN-PNP transistor pairs in an SCR (silicon controlled rectifier) configuration coupled via Schottky barrier diodes (SBDs) to associated bit lines A word select circuit is connected to the NPN emitters, and a write enable (WE) circuit is connected to the PNP emitters. A row of memory cells is provided in parallel between the corresponding output lines WB (word bottom) of the word select and WT (word top) of the write enable circuits. The write enable circuit allows the lowering of the potential of the PNP emitters to turn off the PNP transistors.