Clocked PLA with Dummy Circuit Forming Clock Pulse for Inter Array Driver with Worst Case Delay
Original Publication Date: 1981-Nov-01
Included in the Prior Art Database: 2005-Feb-12
In a PLA with clocking to transmit the output of the AND array to the input of the OR array, a clock signal is generated by a chain of dummy components of the PLA. As logic signals propagate through a particular path in the AND array, a timing signal propagates through the path formed by the dummy components. The dummy path has the same number and type of components as the longest logical path through the AND array, and it thereby provides a timing signal that is appropriate for the longest or worst-case delay. The dummy components that form the clocking pulse are subject to the same variations in manufacturing as other components on the same chip, and the timing signal is thus adjusted to correspond to the delays of the associated AND array.