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Layout of a High Performance CFET Device Configuration Disclosure Number: IPCOM000053943D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-12

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Kraft, WR Moore, VS Stahl, WL Thoma, NG [+details]


In high power CFET circuits, such as off-chip drivers, it is necessary to get the output of the circuit up to some minimum value as quickly as possible, and slowly bring the level to a higher value for the purpose of providing noise tolerance. This has been done in the past using two devices in parallel, an enhancement device and a depletion device. The enhancement device attains the initial value, and the depletion device provides the noise margin.