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Oxide Nitride Dual Insulator Process for Memory Metallization; Large Small Via Etch Sequence Disclosure Number: IPCOM000053996D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-12

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Related People

Logan, JS Schwartz, GC Standley, CL [+details]


In one approach for fabricating FETs using polyimides, a low temperature lift-off matrix is used to pattern the second level metal. This lift off matrix cannot withstand the temperature generation if an RF sputter cleaning process is used just prior to second metal evaporation. Without such RF sputter cleaning, high interlevel "via" resistance is typically experienced due to the native oxide which remains on the aluminum surface.