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Redundancy Scheme for High Speed Random Access Memories Disclosure Number: IPCOM000054012D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-12

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Malaviya, SD [+details]


A redundant word or bit line in a high-speed random-access memory (RAM) is automatically switched in place of a defective line by a single control pulse, with very little chip power, size or delay penalty. The input address is set to the defective word line and a "set" pulse is applied to the chip to permanently deactivate the defective word/bit line and encode the address of the defective line into the redundant line. This scheme is also valid for multiple redundancy.