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Error Detection for Memory with Partially Good Chips

IP.com Disclosure Number: IPCOM000054026D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Forsberg, RA Kerrigan, M Shen, WW Taylor, JM [+details]

Abstract

A memory having 32 data bits and 8 check bits is made up of four modules that have either of two arrangements of three partially good chips? either 4, 4 and 2 or 4, 4, and 3 good bits per chip. Connections between the modules and a conventional odd weight error correction code (ECC) circuit are arranged so that either module type can be used in any of the four module positions of the memory and so that any number of errors in a single chip will be detected. This features protects against circuit faults that disable an entire chip.