Browse Prior Art Database

Up/Down Counter with Gated Clocks

IP.com Disclosure Number: IPCOM000054064D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Moen, DN Thomas, GC [+details]

Abstract

The gated clock up/down counter, as shown in the figure, achieves counter hardware cell reduction, making possible incorporation of additional logic in the circuit module with consequent cost saving.