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Up/Down Counter with Gated Clocks Disclosure Number: IPCOM000054064D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

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Moen, DN Thomas, GC [+details]


The gated clock up/down counter, as shown in the figure, achieves counter hardware cell reduction, making possible incorporation of additional logic in the circuit module with consequent cost saving.