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Layout of MTL Memory Device Disclosure Number: IPCOM000054084D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

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Howard, DD Wiedmann, SK [+details]


This layout eliminates excessive area of the MTL (merged transistor logic) memory cell implemented in a bipolar process having p/+/ polysilicon base contacts and deep trench isolation and without a top N /+/ region butting against the trenches.