Browse Prior Art Database

Layout of MTL Memory Device

IP.com Disclosure Number: IPCOM000054084D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Howard, DD Wiedmann, SK [+details]

Abstract

This layout eliminates excessive area of the MTL (merged transistor logic) memory cell implemented in a bipolar process having p/+/ polysilicon base contacts and deep trench isolation and without a top N /+/ region butting against the trenches.