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Driver Receiver Based on AND Gate

IP.com Disclosure Number: IPCOM000054100D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Herrell, DJ [+details]

Abstract

In the testing of circuits, and particularly Josephson device circuits, a circuit is required which will either send or receive a logic signal at a predetermined time to/from a chip-under-test. This drive/receive circuit should terminate a line correctly when in the receive mode and deliver approximately the correct rise-time pulse when in the drive mode. Circuits based on AND gates are shown in Figs. 1A and 1B. Both of these operate in a similar fashion. Both circuits use interferometers Q, and are connected to the chip-under-test via the terminal marked PORT. The number within the interferometer indicates the number of junctions in the device. For example, interferometer Q4 in Fig. 1A is a two-junction interferometer.