Browse Prior Art Database

Josephson Loop Decoder

IP.com Disclosure Number: IPCOM000054104D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Faris, SM [+details]

Abstract

Fig. 1 shows a prior-art decoder usable in Josephson technology which comprises Josephson junctions J1-J7. Because the decoder loops operate in a self-resetting mode by choosing R(D) sufficiently small a short pulse generator 10 is required to start decoding. In the circuit of Fig. 2, the first stage of the decoder has been modified so that the decoder loops operate in a latching mode. This is accomplished by choosing R(D) large enough. This modification eliminates the need for both pulse generator 10 and the reset gates J6 and J7.