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Integrated Logic Cell Array Layout

IP.com Disclosure Number: IPCOM000054234D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Helwig, K [+details]

Abstract

The density and/or the wiring capabilities of a merged transistor logic (MTL) array can be improved by placing MTL cells in the X and Y directions adjacent to a common injector region. Such an arrangement is practicable, since vias between different metallization levels above silicon contacts are possible.