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Dynamic Memory Refresh Scheme for Transparent Refresh Disclosure Number: IPCOM000054254D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-13

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Aaron, RT [+details]


Most processor dynamic memory systems require memory operating with a cycle time which is one half of the processor instruction cycle time in order to accomplish transparent refresh. The processor accesses memory during one half of the cycle and allows a refresh of the memory during the other half. This approach requires unnecessarily fast and expensive dynamic random-access memories. Described below is a scheme which allows slow and inexpensive random-access memories to be employed with minimal impact on processor throughput.