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Polysilicon Merged Transistor Logic Device

IP.com Disclosure Number: IPCOM000054301D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Feth, GC Weidmann, SK [+details]

Abstract

Merged transistor logic (MTL) devices, as described in (*), use a p polysilicon base area that completely surrounds the collectors. An improvement to the structures of (*) using self-alignment techniques and which further includes a substantial reduction of parasitic silicon area has been achieved and embodied in a comb-like structure, as shown in Fig. 1.