Browse Prior Art Database

Fabrication of Multiple LSI Silicon Chip Modules

IP.com Disclosure Number: IPCOM000054308D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Ho, CW Sampogna, M Zirinsky, S [+details]

Abstract

In packaging of high speed chips 8 on a module 7 (Fig. 1), it is imperative for the package to possess a very low value of inductance in its power supply paths to satisfy maximum switching current requirements of chips 8. In a prior chip carrier of the variety shown in Fig. 1, a metal substrate 12 is shown which serves as a ground plane. Several vertical laminated power plane buses 10 are inserted into slots 14 in substrate 12. Each bus 10 is composed of a plurality of parallel power planes in the form of metal sheets 11 laminated with thin films of dielectric material 13, providing insulation as shown in Fig. 2A, which is a side view of a single power plane 11 with contact tabs 6 and power tap tab 21. The power plane 11 is shown in a plan view in Fig. 2B.