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Self Aligned Silicon MESFET Process

IP.com Disclosure Number: IPCOM000054310D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Dumke, WP Fowler, AB Rupprecht, H [+details]

Abstract

A process to make a high density, self-aligned MESFET is described. A silicon wafer with oxide trench isolation and n and p+ layers on psilicon using epitaxy, implantation or diffusion, shown in Fig. 1, is prepared by conventional methods. A SiO(2) film then is grown over the p+ region and after lithography it is left only over the gate region. RIE (reactive ion etching) and chemical etching are used to define a mesa as shown in Fig. 2.