Faster Non-Inverting Sense Bus For Josephson Memory Arrays
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-13
In this article, a noninverting sense bus is shown. It combines all the features of inverting sense bus circuits plus faster operating speed, i.e., it helps in achieving faster access time. The present scheme shown in Fig. 1 incorporates the waveform transition detector circuit shown in U.S. Patent 4,149,097 to achieve a selfresetting mode of operation.