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This technique provides a drive scheme for VMOS-FET power transistors which furnishes isolation from the VMOS-FET and allows the use of a multi-secondary transformer to drive more than one VMOS-FET.
English (United States)
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Transformer Isolated VMOS-FET Drive Scheme
This technique provides a drive scheme for VMOS-FET power transistors
which furnishes isolation from the VMOS-FET and allows the use of a multi-
secondary transformer to drive more than one VMOS-FET.
When an input pulse is present, transistor Q1 is turned on and held out of
saturation by diode D1. With Q1 in the on state, transistors Q2 and Q3 are both
turned on, applying voltage to the primary winding 2 of transformer T1 which
allows current to flow in the winding 2. Diodes D2 and D3 are both off. The
secondary winding 3 of T1 applies a voltage to the network including diode D4
and resistor R6 which forward biases D4. The gate of the VMOS-FET is biased
positive, causing it to turn on.
When the input pulse is removed, Q1, Q2, and Q3 turn off. The polarity of
winding 2 reverses, turning D2 and D3 on and discharging the energy stored in
the primary inductance and leakage inductance of T1. Simultaneously, the
voltage across winding 3 also reverses, biasing D4 to an off condition. The gate
of the VMOS-FET is returned to ground by R6 which turns off the VMOS-FET.
Resistor R5 damps any ringing in winding 2.
A multi-secondary transformer csn be used to drive more then one VMOS-
FET, which allows series or parallel operation with enough current to drive the
gate capacitance of paralleled VMOS-FET transistors. This allows voltage
isolation between secondaries. The symmetry of the drive circuit provides
bidirectional transformer p...