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A VMOS structure has improved bilateral characteristics when a graded boron diffusion is formed in a polysilicon gate used with a normally graded boron channel region.
English (United States)
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Flat Channel Sensitivity VMOS Structure
A VMOS structure has improved bilateral characteristics when a graded
boron diffusion is formed in a polysilicon gate used with a normally graded boron
For example, when in a one-device memory cell, the roles of source and
drain regions in a field-effect transistor formed in a V-groove having a normally
graded doped channel are reversed, the reverse threshold being different from
the original or forward threshold.
In the figure, a one-device memory cell is illustrated which includes a silicon
substrate 10 having a P+ type conductivity over which is grown a P-type epitaxial
layer 12 having a graded doping with a buried N+ region 14 formed at the
interface 16 between substrate 10 and layer 12. An N-type region 20 is formed
within P-type layer 12. The Vgroove 22 is formed at the surface of N-type region
20 which extends through N-type region 20 and graded P-type layer 12 with its
apex located within the N+ region 14. A thin insulating layer 24 is disposed on
the faces or walls of the V-groove, and a thick insulating layer 26 is disposed on
the upper or planar surface of the epitaxial layer 12. Formed within groove 22
over the thin insulating layer 24 is a layer of conductive polysilicon 28. Layers 24
and 28 are preferably oxides. As is known, the basic threshold equation of a
devices is: (see original) where tox is the gate oxide thickness, Epsilon is the
oxide dielectric constant, Qe is the effective charge at the oxide-silicon interface,
Delta W(F) is the work function difference between the gate conductor and the
silicon substrate, Psi (S) is the band bending at the silicon surface, N(a) is the
donor doping level in the silicon substrate, q is the charge on the electron, and
V(S-SUB) is the potential difference between source and...