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Edge-Selection Circuit Disclosure Number: IPCOM000054483D
Original Publication Date: 1980-Feb-01
Included in the Prior Art Database: 2005-Feb-13

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Langdon, GG [+details]


This article describes a poll passing arrangement among daisy-chained devices in which the usual low pass elements in the poll pulse sensing portions of each device are replaced by a broader bandwidth edge-triggered D type flip-flop as modified by a NAND gate output. The daisy-chain is utilized for priority employing an asynchronous Select Out/Select In type of priority resolution signal. The Select Out/Select In signal invokes a voltage transition termed an "edge" for identifying the highest-priority user requesting the resource (bus). The highestpriority user is the most "upstream" in the, chain while the lowestpriority user is the most "downstream" in the chain. A CPU generating a Select Out/Select In edge passes it to the highest-priority user.