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Single Polysilicon One-Device FET Dynamic Memory Cell With Junction Storage Capacitor Underneath The Field Oxide

IP.com Disclosure Number: IPCOM000054511D
Original Publication Date: 1980-Feb-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Chao, HH Dennard, RH [+details]

Abstract

A one-device FET dynamic memory cell is described which has a junction storage capacitor underneath the field oxide. In this new arrangement, the N/+/ layer under the field oxide provides an additional level of interconnection in the cell, therefore improving the wirability within the cell and decreasing the cell size. A cross-section of the memory cell using this concept is shown in Fig. 1. The junction capacitor is fabricated at the very beginning so that the anneal and drive-in cycles can be optimized for the p/+/ and n/+/ junction 10 without other consideration. Both ion implantations and/or diffusions can be used to fabricate the p/+/ - n/+/ junction 10 capacitor. Fabrication of the devices is then completed using normal n-channel silicon-gate processing.