High Performance Package with Conductive Bonding to Chips
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13
There are two major constraints to today's approaches to packaging high performance semiconductor technology. Regarding thermal dissipation, the total thermal resistance path from the heat source, the chip, to the heat sink sets an upper limit to the amount of power a chip may be allowed to dissipate. This power limit can often limit the circuit speeds the chip can attain. Therefore, circuit performance and, in the case of a computer, machine cycle speed can be improved by improving the thermal dissipation characteristics of the package. Regarding electrical power distribution, the total circuit impedance, both DC and AC, between the power supply and the chip, sets an upper limit to the noise tolerance and the circuit speeds the chip can attain.