Browse Prior Art Database

Macro Modelling of a Most NAND Gate

IP.com Disclosure Number: IPCOM000054635D
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Hsieh, HY Rabbat, NB [+details]

Abstract

Discussed here is a procedure for macro-modelling of NAND gates. If the sum of the individual currents of parallel switching transistors, I(1), is considered constant during the fixed time interval delta t, for a given set of input conditions, we can write: See Original (pages 4533-4539).