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Chip Image for Enhanced Physical Macro Placement Disclosure Number: IPCOM000054640D
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13

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Barish, AE Ehrlickman, RL Ferreri, RJ [+details]


In a masterslice, physical macro placement is limited by any wiring blockages which exist in the chip image. This article proposes a chip image which eases the macro placement problem by minimizing chip blockages (Fig. 1).