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This clamp provides accurately controlled temperature-compensated uplevel drive to a dual function current source-column driver. The clamp is temperature compensated by a symmetrical configuration.
English (United States)
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Clamped Array Bit Line Driver
This clamp provides accurately controlled temperature-compensated uplevel
drive to a dual function current source-column driver. The clamp is temperature
compensated by a symmetrical configuration.
An input signal is provided to T1, the output of which turns on or turns off T3.
The collector of T3 falls when T3 is in a conducting state. The reduced collector
potential of T3 is applied to the base of an output transistor T9. In this state, T8
is conducting and T7 is non-conducting. The temperature coefficients for VBE of
T7 and T8 cancel in this state, as well as the temperature coefficients of VBE for
T6 and T9 are cancelled due to the balanced design.
When T1 turns off, T3 turns off, the voltage rises at the collector of T3, which
turns on T9. Again, the temperature coefficients of T6, T7, T8, and T9 for their
respective VBE's are cancelled. In this latter state, T8 is off and T7 is
conducting because the voltage from the collector of T3 is applied through T6 as
a diode to turn on T7.
T2 sets the bias level for T4, which is part of a current switch including T3.
T5 is a clamp for T3.
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