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A method is disclosed that permits the logic function of a three-state bus driver (TSBD) to be modeled for defective and defect-free switching states.
English (United States)
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Three State Bus Driver Logic Model
A method is disclosed that permits the logic function of a three-state bus
driver (TSBD) to be modeled for defective and defect-free switching states.
In LSI manufacturing, the final logic test is an important step to insure the
quality of a logic circuit embodied in a semiconductor device. Since it is
impossible to apply all test patterns in sequences which the logic circuit will be
subject to in use, it is standard practice to analyze the defects that may occur in
manufacturing of a semiconductor device to determine that the chip device does
not contain these predicted defects. The defects are normally represented as
logic gate inputs or outputs stuck at a logical "1" or "0".
The three-state driver does not lend itself to this type of modelling. Besides
having a third logic state (high impedance), defects can cause logic failures of
the output stuck at non-traditional values, i.e., stuck at high impedance, stuck at
not one, etc. The identification of these new defects may be overcome by the
definition of a logic primitive covering a portion of the first state driver.
Fig. 1 shows a three-state driver circuit that may be represented by a logic
primitive, as shown in Fig. 2. An associated transfer function is shown in Fig. 3.
Defects in Fig. 1 may be easily modelled by using common "stuck fault"
In Fig. 1, an open resistor R or transistor T1 or diode D is represented by a
stuck 0 on input A. An open transistor 2 is r...