Browse Prior Art Database

I/2/L/MTL Storage Cell Layout

IP.com Disclosure Number: IPCOM000054662D
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Berger, HH Heuber, K Klink, E Wiedman, SK [+details]

Abstract

Monolithically integrated storage cell with two I/2/L/MTL basic structures cross-coupled in the manner of a flip-flop and each consisting of a lateral PNP transistor T1, T1' and an inversely operated, inverting vertical NPN transistor T2, T2' merged therewith. One of the two bit lines B0, B1, used to apply the read/write signals, is connected to each injection region P1, P1' which simultaneously forms the emitter of the lateral transistor T1, T1'. A storage cell is selected by a common word line WL at the emitters of the two inverting transistors T2, T2'. Cross-coupling is effected via conductors M, M' extending between the base of one and the collector of the other inverting transistor T2, T2'.