Browse Prior Art Database

Distributed Clock System

IP.com Disclosure Number: IPCOM000054666D
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Klein, W Najmann, K Rudolph, V Wernicke, F [+details]

Abstract

In VLSI (very large-scale integration) bipolar memory chips, the power consumption in the non-selected state must be very low. For this reason, the various circuits are switched on by means of power gates only at selection time. In addition, the individual circuits are activated in a particular sequence. The combination of power gates and timing leads to a power clock system with a great number of clock lines CL1, CL2, CL3 supplying circuits A, B, C distributed over the whole chip (Fig. 1).