Two Speed Control Storage
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13
This article describes a method for synchronizing micro-instruction execution with instruction access from a linear control storage address space having dissimilar access speeds. The method steps comprise (1) sensing the presence of a pointer in the address field of a currently decoded instruction and (2) inhibiting the system clock by a predetermined amount responsive to a pointer indicating a slower speed store location. A configuration of this type permits partitioning microcode sequences according to their execution speed, and then allocating their residence to counterpart dedicated memories.