Generic Addressing for Interface Bus
Original Publication Date: 1980-Mar-01
Included in the Prior Art Database: 2005-Feb-13
This article describes an apparatus for sharing a single daisy-chained priority selection mechanism among several classes of ports accessing a common bus. For each bus cycle, each available port accesses a local memory in order to ascertain class identity. If the identity is affirmative, the poll request is daisy-chained among the class members. The port having the highest priority in the class responds to the poll. If the port is not a member of the class, it does not interfere with the chain.