Sense Latch With Adjusting Series Impedance
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13
A sense latch for memory cells is provided with resistive decoupling means at the high voltage bit line side of the latch to reduce its susceptibility to being discharged while the other, or low voltage, bit line side of the latch is readily discharged. This latch utilizes depletion-mode devices for decoupling or isolating the bit lines from the latch without requiring a high voltage pulse.