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Self-Aligned IGFET with Silicon Dioxide Isolated Source and Drain

IP.com Disclosure Number: IPCOM000054797D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Anatha, NG Horng, CT Konian, RR Matick, RE [+details]

Abstract

The performance of an insulated agate field effect transistor (IGFET) device can be improved by reducing the capacitances associated with the source and drain junctions. In the usual method of fabrication of these devices the capacitance of the sidewall as well as the bottom wall of these junctions adds to put a limit on the density and performance of the integrated circuit chip. A method by which the bottom wall and sidewall capacitance of the source and drain junctions can be eliminated would reduce capacitance. In the structure of such integrated circuit each active device is completely confined to the single crystal region. A memory chip built using this structure will have very low bit line capacitance as compared to regular methods of fabrication.