Browse Prior Art Database

Process for Fabrication of Shallow and Deep Silicon Dioxide Filled Trenches

IP.com Disclosure Number: IPCOM000054798D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Lillja, HV Horng, CT [+details]

Abstract

The device dielectric isolation employed is achieved by using a shallow I Mum oxide trench to separate the base and collector contact regions an a deep 4 Mum oxide trench to surround the transistor. At the bottom of the deep trench a channel stop formed by boron implantation prevents inversion of the lightly doped P- substrate.