Browse Prior Art Database

Dynamic Random Access Memory Cell Employing V-Groove Connection to Buried N+ Layer and Optional Oxide Capacitor

IP.com Disclosure Number: IPCOM000054810D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Chang, TS Ogura, S Walker, WW [+details]

Abstract

A buried N+ storage capacitor connected to a surface transfer device via a V-groove provides improved reliability over the conventional VMOS dynamic conventional double polysilicon random-access memory cell. The dynamic random-access memory cell illustrated in Fig. 1 employs a conventional surface MOSFET as a transfer device and a diffusion along the wall of a V-groove to guide charge to a buried N+ capacitor where it is stored. Unlike the VMOS dynamic random-access memory cell [1], it does not have a MOSFET on the V-groove wall, and unlike BOMOS [2], no buried oxide or polysilicon epitaxial layer is used. Instead, the epitaxial layer is entirely single-crystalline, and the N+ impurity along the V-groove wall is implanted after it has been partially etched.