Browse Prior Art Database

Restore Scheme

IP.com Disclosure Number: IPCOM000054837D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Heuber, K Weidmann, SK [+details]

Abstract

In the illustrated circuit diagram, the cells are arranged in an array at the crossings of word lines WL and bit line pairs BL0, BL1. The cells consist of transistors in MTL (merged transistor logic) technology.