Forced Test Path Signal for Testing Embedded Arrays
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13
LSI chips used to implement complete CPUs also comprise embedded arrays. Problems arise when these arrays are to be tested, because their inputs and outputs are not accessible from the chip pins. Generally, the path from a chip pin to an array leads through one or several gates and registers which are controlled by clock pulses at different times. The testing problem could be solved, for example, by implementing the logic surrounding the array in accordance with level sensitive scan design (LSSD) rules. However, such an approach would entail a great number of additional circuits and excessively long testing times.