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Dynamically Loadable Incrementer Decrementer

IP.com Disclosure Number: IPCOM000054859D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Cassidy, BM [+details]

Abstract

This circuit is a master-slave register that can be repeated N times to make an N bit incrementer-decrementer. A high level of circuit density is achieved with this circuit because increment-decrement functions are integrated into storage functions.