Browse Prior Art Database

Decoding Circuit

IP.com Disclosure Number: IPCOM000054860D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Rosenbluth, W Williams, T [+details]

Abstract

Conventional FET (field-effect transistor) logic circuits often require both true and complement input signals to carry out their logical functions. This can be attained only with the inclusion of extra inverter circuits which occupy additional space and dissipate additional power. A circuit technique is disclosed which eliminates the necessity for providing extra inverters to generate the complement signals from the true signals available for input to the logic circuits.