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Fabrication Procedure for MOSFET Logic Integrated Circuit with very Thin Gate Oxide

IP.com Disclosure Number: IPCOM000054916D
Original Publication Date: 1980-Apr-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Chao, HH Wordeman, MR [+details]

Abstract

This article describes a fabrication procedure for the n-channel MOSFET logic circuit with very thin gate oxide (approx. 10 nm) to achieve improved completion mode device threshold voltage control and device characteristic. The threshold voltage V of a long channel MOSFET is expressed as v(t) = Phi + 2 Phi(F) - Q(ox)/C(ox)-Q(B)/C(ox) (1). where Phi(MS) is the work function difference of the gate and the substrate, Phi(F) is the substrate Fermi potential, Q(ox) is the effective oxide charge, Q(B) is the surface depletion layer charge, and C(ox) is th gate oxide capacitance. For a typical (p+) polysilicon gate device, Phi (MS) approx./- -1V, 2 Phi (F) approx./- o.6V and Q(ox)/q approx./- x10/10/ cm. Normally, both depletion-mode devices and enhancement-mode devices are required for high performance logic.