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Self Correcting Switchtail Ring Counter

IP.com Disclosure Number: IPCOM000054970D
Original Publication Date: 1980-May-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Norgren, KS Tadehara, D [+details]

Abstract

Fig. 1 shows a six-stage ring counter. The counter is referred to as a switchtail ring counter in that it normally has only the states listed in Fig. 2. The counter starts with a 0-bit in each stage S(0) through S(5) of the counter. As the S(5) bit is clock out of the counter, it is fed back to the S(0) stage through OR 10 and inverter 12. If the S(5) bit is a 1, a 0 will be loaded into the S(0) stage. Conversely, if the S(5) bit is a 0, a 1 will be loaded into the S(0) stage. The contents of the counter for its twelve possible legal states are shown in Fig. 2.