Early Detection of Invalid Program Counter State
Original Publication Date: 1980-May-01
Included in the Prior Art Database: 2005-Feb-13
Data input on lines 1 to program instruction counter register 2 is monitored by hard-wired logic 3 to recognize an invalid input and enable setting the register 2 by means of gate 4 only upon recognizing a valid input combination. An invalid input immediately raises an exception prior to loss of the previous information in register 2, which can be used to detect the source of the invalid input.